1. Field of the Invention
The present invention relates to a method of manufacturing a complementary metal-oxide semiconductor device, and more particularly to a method of manufacturing a complementary metal-oxide semiconductor(hereinafter simply referred to as "CMOS" device) for a n-channel element and a p-channel element respectively having a low threshold voltage in a semiconductor device, which is convenient to manufacture.
2. Description of the Prior Art
Generally, it is required to provide special performances to an integrated circuit due the high integration and increased complex functionality of semiconductor devices. For this purpose, a CMOS transistor having an improved N-type MOS transistor and an improved P-type MOS transistor has been developed. The improved N-type MOS transistor and P-type MOS transistor have a relatively low threshold voltage in regard to a specific region in the semiconductor device, and are respectively named Low Vt N-type MOS transistor and Low Vt P-type MOS transistor. The Low Vt N-type MOS transistor and the Low Vt P-type MOS transistor minimize voltage drop between a source and a drain in the MOS transistor. Consequently, the characteristic of the semiconductor device employing the CMOS transistor is enhanced.
In order to form the Low Vt N-type MOS transistor and the Low Vt P-type MOS transistor, however, an additional mask forming process and an additional ion implantation process must be applied to a region of the Low Vt N-type MOS transistor and a region of the Low Vt P-type MOS transistor, respectively. Consequently, the yield of the CMOS transistor is decreased, the manufacturing cost of the CMOS transistor is highly increased.